In the field of integrated circuit devices, and in particular in the field of integrated circuit devices for use in automotive applications, it is known to use error-correction codes (ECCs) to protect data stored within RAM (Random Access Memory), particularly to protect against “soft errors” within the data caused by error events such as, for example, alpha radiation, atmospheric neutrons, etc. Examples of such error-correction codes are extended Hamming codes, Hsia codes and similar linear codes, which provide single-bit error correction and double bit error detection.
As process technologies have evolved and been scaled down to nanometers, a single error event (e.g. caused by a single alpha or neutron particle) can cause multiple neighbouring bit cells within RAM to change state, and therefore become corrupted. Thus, the single-bit error correction provided by traditional ECC techniques alone is insufficient to protect against such error events. To overcome this problem, it is known to interleave data words stored within a block of RAM. In this manner, neighbouring data bits of a data word are not stored adjacent to one another within the block of RAM. This technique is typically denoted as a multiplexing (MUX) factor. For example, FIG. 1 illustrates a simplified block diagram of RAM 100 with a MUX factor ‘4’. Accordingly, four data words 110, 120, 130, 140 (each comprising four bits for the simplified illustrated example) are interleaved into a single row 150 of bit cells of the block of RAM 100. In this manner, for a block of RAM with a MUX factor ‘4’, such as the block of RAM 100 illustrated in FIG. 1, every fourth data bit stored within a row of bit cells belongs to the same data word. If an error event occurs, for example by way of an alpha particle or neutron hitting the block of RAM, such that up to four adjacent bit cells within a single row become corrupted, only one bit in any data word will be corrupted. Thus, in this manner, the error is capable of being corrected by traditional ECC single-bit error correction techniques. Furthermore, and as illustrated in FIG. 2, by passing data read from a block of RAM 100 with a MUX factor 4 through a traditional ECC functional block 200, multi-bit error events that corrupt up to four adjacent bit cells within a single row 150 may be protected against.
However, with the continued shrinking of process technology and feature size, RAM bit cells are becoming ever smaller, with the number of adjacent RAM bit cells that may be affected by a single error event becoming greater. Accordingly, there is a demand for data stored within a block of RAM to be protected against multi-bit error events that corrupt greater numbers of adjacent bit cells within a single row of RAM bit cells.
One solution to this problem is to use an ECC code that is able to correct, say, two errors, instead of the single-error codes. In this manner, when used in conjunction with a RAM having a MUX factor of ‘4’, multi-bit error events that corrupt up to eight adjacent bit cells within a single row may be protected against. However, a problem with this approach is that the use of such multi-error correction codes is much slower than the single-error codes, making such multi-error correction codes impractical from the point of view of performance.
Another solution to this problem is to increase the MUX factor for the block of RAM, for example to use a block of RAM with a MUX factor of ‘8’, whereby data bits of eight data words are interleaved into a single row of RAM bit cells. In this manner, every eighth data bit within a row belongs to the same data word. When implemented with traditional ECC single-bit error correction techniques, multi-bit error events that corrupt up to eight adjacent bit cells within a single row may be protected against.
A problem with this solution is that it places significant constraints on the physical implementation of the block of RAM. Whilst such constraints may be accommodated with large blocks of RAM, for smaller blocks of RAM such constraints make this solution impractical. For example, suppose a block of RAM is required to comprise 32-bit words and, say, 256 words. If this block of RAM is implemented with a MUX factor of 4, the block of RAM will comprise a matrix of RAM bit cells comprising (32*4=128) rows (bit-lines), and (256/4=64) columns. Thus, the matrix of RAM bit cells comprises a factor 2 difference between dimensions. However, if the block of RAM is implemented with a MUX factor of 8, the number of rows required becomes 32*8=256, and the number of columns becomes (256/8=32). Consequently, the matrix of RAM bit cells comprises a factor 8 difference; 256 rows×32 cols. As a result, this RAM array will comprise a thin rectangle on the silicon, resulting in poor area efficiency and poor timing. Typically, a figure-of-merit for the dimension of the matrix of RAM bit cells may be considered as: (#bit*MUX_FACTOR) should not differ more than a factor of between 2 and 4 of the (#words/MUX_FACTOR).